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SOCELL PROJECT GOAL
SOCELL PROJECT GOAL
To develop a new ASIC that enables more compact, effective, and affordable Battery Management Systems, with enhanced HW-based diagnosis, wireless communications, fault tolerant and active balancing capabilities.
HIGHLIGHTS
HIGHLIGHTS
Developing an ASIC in CMOS tech for a Battery Management System (BMS)
Targeted for cell-level integration in large battery cells in next-generation battery electric vehicles (BEVs)
A publicly funded project between industry and academia - CTAG and UVIGO
Aiming to enhance cell trazability, monitoring, diagnosis, and safety
Enabling re-configuration, wireless communications, and on-board EIS
A CELL-LEVEL ASIC FOR BMS IN BEVs
A CELL-LEVEL ASIC FOR BMS IN BEVs
SOCELL creates technology for optimal integration of advanced BMS in large cells
SOCELL creates technology for optimal integration of advanced BMS in large cells
BRIDGING THE GAP BETWEEN INDUSTRY AND ACADEMIA
BRIDGING THE GAP BETWEEN INDUSTRY AND ACADEMIA
SOCELL is a collaborative project between Universidade de Vigo and
Centro Tecnológico de la Automoción de Galicia (CTAG)
SOCELL is a collaborative project between Universidade de Vigo and
Centro Tecnológico de la Automoción de Galicia (CTAG)
KEY INNOVATIONS FOR ADVANCED BATTERY MANAGEMENT
KEY INNOVATIONS FOR ADVANCED BATTERY MANAGEMENT
SOCELL focuses on the development of key technology innovations at ASIC level
SOCELL focuses on the development of key technology innovations at ASIC level
NFC comm.
NFC comm.
Integration of NFC tags in cells and NFC readers and writers in BMS to improve cell trazability, storing key battery data in accordance with the Battery Passport inititative
LiFi comm.
LiFi comm.
Investigating the opportunities in wireless communication for BMS based on visible light communication through LiFi technology
Multi-Project Wafer (MPW)
Multi-Project Wafer (MPW)
ASIC prototypes manufactured through MPW services provided by the EUROPRACTICE program
On-board EIS
On-board EIS
Developing technologies to enable electrochemical impedance estimation on-board and at cell level
Re-configurability
Re-configurability
Enabling cell isolation and active balancing, through the integration of power switches that enable cell by-pass and inversion
EXECUTIVE SUMMARY
EXECUTIVE SUMMARY
There is increasing interest in developing compact and cost-efficient Battery Management Systems (BMS) for next-generation electric vehicles. These systems aim to provide improved fault tolerance, active balancing functionalities, additional hardware for diagnosis, and wireless communication, which reduces wiring complexity and enhances cell traceability.
There is increasing interest in developing compact and cost-efficient Battery Management Systems (BMS) for next-generation electric vehicles. These systems aim to provide improved fault tolerance, active balancing functionalities, additional hardware for diagnosis, and wireless communication, which reduces wiring complexity and enhances cell traceability.
To meet these requirements, a new Application-Specific Integrated Circuit (ASIC) has been designed and fabricated through the EUROPRACTICE program for integration into a system-on-cell BMS. The ASIC is developed using a staged approach, with parallel implementation and validation of key functionalities in proof-of-concept circuits.
To meet these requirements, a new Application-Specific Integrated Circuit (ASIC) has been designed and fabricated through the EUROPRACTICE program for integration into a system-on-cell BMS. The ASIC is developed using a staged approach, with parallel implementation and validation of key functionalities in proof-of-concept circuits.
The target system is designed to incorporate current, voltage, and temperature monitoring, LiFi-based wireless communication, NFC tag reading for cell identification, on-board impedance measurement, and the ability to reconfigure cells' interconnections for fault isolation and balancing.
The target system is designed to incorporate current, voltage, and temperature monitoring, LiFi-based wireless communication, NFC tag reading for cell identification, on-board impedance measurement, and the ability to reconfigure cells' interconnections for fault isolation and balancing.
SOCELL PROJECT STATUS
SOCELL PROJECT STATUS
The first two prototypes (Analog and Analog-Digital) and the PoC circuits for advanced functionalities have already been designed, manufactured, and validated - working now on the full system integration in the final production ASIC
The first two prototypes (Analog and Analog-Digital) and the PoC circuits for advanced functionalities have already been designed, manufactured, and validated - working now on the full system integration in the final production ASIC
Any question? Interested in collaboration?
Any question? Interested in collaboration?
You are welcome to contact us!
SoCell ASIC architecture is part of the patent ES2875953 granted to CTAG
This work is part of the R&D projects TED2021-131718B-C21 and TED2021-131718B-C22, funded by MICIU/AEI/10.13039/501100011033/ and by the “European Union NextGenerationEU/PRTR”.
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